In our product teardowns, we gather a series of metrics for product profiling and comparison. Some metrics focus on system characteristics such as total silicon area, total system semiconductor storage capacity, and total connection count. Other metrics reflect more subtle aspects of electronics assembly such as connection density, average component I/O count, and silicon tiling density. Taken as a whole, the metrics allow deeper comparison and benchmarking across multiple disciplines and multiple products. Key metrics we gather on products are described below along with their definitions and what they tend to say about the system under study. Most metrics can be used both in comparing similar products for benchmarking purposes or for quantifying differences in levels of complexity between dissimilar product types. Data fall into two categories; either "raw" measured data or ratios of these measured data sets.
Total Silicon Area : This metric describes the total area of silicon as measured from X-ray or direct measurement of ICs. The area is an expression of the enclosed bare die area and excludes packaging area. The aggregate silicon area is a good benchmark to show how integrated a design might be when making comparisons to similar systems. Total silicon area also reflects the major cost driver for most systems we examine.
Silicon Tiling Density : Ratio of Total Silicon Area to total printed circuit board "projected" area (i.e. the simple board area and not the cumulative surface area of both sides of the board). This metric directly reflects the level of efficiency and aggressiveness in integrated circuit packing and placement. Single digit Silicon Tiling Density is typical but silicon coverage of 10% - 20% has been seen in some of the most advanced products we have examined. Higher Tiling Densities often correspond with the use of chip scale packaging (CSPs) or other small form-factor IC packaging technologies. High density circuit boards are also often a supporting technology.
Number of Parts : Total component count including ICs, passives, modules, connectors, etc., each separated out in our reporting.
Number of Connections : The total number of connections corresponds to the total number of interconnects introduced by the aggregate component set and reflects any electrical connection observed (solder joints, adhesive interconnect, or connector terminal interfaces).
Opportunity Count : Opportunity Count is the total number of parts plus the total number of connections; the name reflects that each of these constituent elements represents an opportunity for failure. A high opportunity count means more complex and riskier electronics assembly.
Average Pin Count (APC) : Ratio of total number of component terminals to total number of parts, at the system level. This metric reflects the "average" terminal complexity of the components and often provide a signature of integration level and/or "digital-ness" of the overall product. Low APCs reflect a high number of discretes or other low-pincount devices often characteristic of analog circuitry. Conversely, high APCs are characteristic of highly integrated, high-pincount assemblies, often those composed largely of digital integrated circuits.
Connection Density : This metric is a ratio of the total Number of Connections to total printed circuit board assembly area, in units of connections per sq. inch. The metric provides data related to the Silicon Tiling Density above, but with an emphasis on complexity of I/O interconnect. For example, with a fixed Connection Density, high tiling density of low-pincount memory chips is more readily achieved than comparable silicon tiling of high pincount logic.
Part Density : This metric is a ratio of the total Number of Parts to total printed circuit board assembly area, in units of components per sq. inch. The metric provides data related to the Silicon Tiling Density and Connection Density as described above, but with an emphasis on density and complexity of component packing efficiency. For example, low Part Density of high-pincount devices can pose an equal challenge in Connection Density to high Part Density of low-pincount devices. High Part Density does reflect challenges in surface mount assembly in terms of (typically) precision of placement, number of placements, and engineering of part clearances.
Routing Density (heuristic estimate) = 3*(Average Pin Count)*the square root of Part Density. The Routing Density metric is a empirically derived relationship that characterizes the wiring density of the interconnect used to support the interconnection of components in a planar electronic assembly (i.e. the circuit board). Architectural issues such as bussing or other factors affecting the regularity of wiring impact the actual Routing Density needed to support a given application, but the metric provides a ready measure of wiring complexity.
Cost Estimation Process: Overview and Discussion